1. Field of the Invention
The present invention relates to a pattern data density inspection apparatus for inspecting the density of mask layout data in a pattern layout for a semiconductor device.
2. Background Art
Recently, with the progress in miniaturization of semiconductor devices, tolerances in dimensional accuracy of the layout design, that is to say, manufacturing error tolerances such as in the width and pitch of the line pattern, in the contrast, and in the dimensions in the height direction have become small so that if there is not sufficient flatness in the interlayer insulation film between multilayer wiring, manufacture of the semiconductor device becomes impossible. That is to say, as shown in FIG. 6, the surface of an interlayer insulation film I1 on an upper portion of a wiring pattern P1 formed on a substrate S surface, is formed naturally higher than other regions. In the case where a next layer wiring pattern is formed on the surface of this interlayer insulation film I1, reliability is impaired due for example to the wiring pattern of the next layer becoming severe at a step portion E1 of the interlayer insulation film I1, and the width of the pattern wiring being formed narrow, so that with the passing of time, this narrow portion becomes disconnected by electro-migration.
Furthermore, the surface shape of the interlayer insulation film formed on the upper portion of the pattern wiring, changes due to the value of the wiring width. As shown in FIG. 7, a step E2 of an interlayer insulation I2, formed on the substrate S surface, compared to the step E1 shown in FIG. 6, has a restrictive shape with respect to formation of the next wiring pattern. Therefore, in order to prevent the occurrence of the above mentioned disconnection and the like of the wiring pattern of the next layer and the upper layer, a planarization technique for the interlayer insulation film involving CMP (Chemical Mechanical Polishing) or the like is used. Here, FIG. 6 (and FIG. 7) are sectional views of a semiconductor device showing a configuration example of an interlayer insulation film I1 (interlayer insulation film I2) formed when a pattern P1 (pattern P2) is on the bottom layer.
However, with the above mentioned planarization technique, the interlayer insulation film cannot be completely planarized. That is, as shown in FIG. 8, in the case where the width of the wiring pattern P1 is narrow, the difference in level is removed. However, in the case where the width of the wiring pattern P2 is wide, a small difference in level remains This difference in level is referred to as a global difference. Therefore, while with the dimensional accuracy in the layout design of conventional semiconductor devices, it is possible to cope with the remaining global difference, with the progress of miniaturization, this remaining difference in level has become a shape having a height which cannot be disregarded. Here, a distance between the surface of an interlayer insulation film I3 on an upper portion of the wiring pattern P2, and the surface of an interlayer insulation film I3 on an upper portion of the substrate S, that is to say the height of the global difference, is made dg. Here FIG. 8 is a sectional view of a semiconductor device showing a configuration example of an interlayer insulation film I3 which is formed when a pattern P1, a pattern P2 and a pattern P3 are the lower layer.
For example, as shown in FIG. 8, in the case where the wide wiring patterns P2 and P3 are formed adjacent, the interlayer insulation film I3 is formed with a skirt with a difference in level, on the upper portion of the wiring pattern P2 and the wiring pattern P3. Hence this is formed with a thickness including the height of the global difference, on the surface of the substrate S between the wiring pattern P2 and the wiring pattern P3. Consequently, the thickness of the interlayer insulation film for the substrate surface becomes non uniform.
Therefore, the etching depth in the interlayer insulation film I3, for a contact hole CT1 for a dispersion layer D1 formed on the substrate S surface, and a contact hole CT2 for a dispersion layer D2 formed on the substrate S surface differs. That is to say, when the contact hole CT2 reaches the surface of the dispersion layer D2, the contact hole CT1 has not yet reached the surface of the dispersion layer D1.
Consequently, in the case where the etching of the interlayer insulation film I3 is continued so that the contact hole CT1 reaches to the dispersion layer D1, over etching occurs with respect to the contact hole CT2. As a result, the contact hole CT2 reaches the dispersion layer D2 surface and the dispersion layer D2 surface is then etched. Hence lattice defects occur bringing about a deterioration in electrical characteristics such as a drop in the breakdown resistance of the dispersion layer D2.
Since as mentioned above there is a limit to the planarization technique, it has been considered in the stage for layout design of the semiconductor memory device, to detect congested regions (pattern data density error regions) with wide wiring patterns which produce this global difference, to thus prevent the occurrence of global differences. For example the graph shown in FIG. 9 shows the experimentally obtained relationship between the width (X axis) of isolated aluminum wiring as a wiring pattern, and the height dg (Y axis) of the global difference. The change in global difference shown in the figure for an aluminum wiring width near 400 xcexcm is large. Moreover, if the height is around this height dg, this can be permitted. At this time, in the design rule used for making the graph of FIG. 9, the thickness of the aluminum wiring is 600 nm, and the thickness of the interlayer insulation film is 800 nm.
Furthermore, in the region of a 400 xcexcm square (400 xcexcmxc3x97400 xcexcm), if the area density of the aluminum wiring (the value for the total surface area of the aluminum wiring pattern divided by the area of the region; the pattern data density) becomes greater than 50%, it is confirmed experimentally that the condition is equivalent to the change in global difference for an aluminum wiring width near 400 xcexcm. Furthermore, it is similarly obtained by experiment that when obtaining this area density, aluminum wiring where the wiring width is less than 1.2 xcexcm can be ignored. Based on this result, a chip of a semiconductor device is divided into lattice shape detection regions and the pattern data density in each of the detection regions obtained. Then with a detection range where this pattern data density exceeds 50% as a pattern data density error region, a designer of a layout pattern considers processes to prevent the occurrence of global differences to obtain correction of the wiring pattern. Hereunder is a description of the process for detecting pattern data density error regions.
A description is given of a conventional pattern data density inspection apparatus based on the figures. FIG. 10 is a block diagram showing the construction of a conventional pattern data density inspection apparatus. A control section 100 reads out layout data for performing inspection, from a layout storage section 101 in which is stored a plurality of layout data, and writes the read out layout data to an input processing section 102 and an output processing section 104, where this is stored. This layout data is wiring pattern data, that is to say a wiring layer data file.
A density computation processing section 103, under instructions from the control section 100, divides the layout data stored in the input processing section 102 into lattice shape detection ranges, and performs pattern data density computations for each of the detection ranges. Furthermore, the density computation processing section 103 judges if the pattern data density for each of the detection ranges is above 50%. At this time, the density computation processing section 103 makes a color for detection ranges in the layout data stored in the output processing section 104, where the pattern data density is above 50%, that is to say the color for regions corresponding to pattern data density error regions, different from that for other normal regions, so that the pattern data density error region of the layout data is clear to a designer who performs correction of the layout. Then under instructions from the control section 100, the output processing section 104 outputs an image showing the pattern data density error region, from a printer (not shown in the figure) provided on the pattern data density inspection apparatus, or displays this on a CRT (cathode-ray tube)(not shown in the figure).
Next is a description of the operation of the conventional pattern data density inspection apparatus, with reference to FIG. 10 and FIG. 11. FIG. 11 is a flow chart showing the operation of the conventional pattern data density inspection apparatus.
In step S100, the control section 100 performs control of the operation of the pattern data density inspection apparatus, in accordance with a program stored in a memory comprising a CPU, a memory and the like. Furthermore, the control section 100 reads out layout data for performing inspection of the pattern data density, from the layout storage section 101, and writes the read out layout data to the input processing section 102 and the output processing section 104. Then, the control section 100 outputs to the density computation processing section 103, instructions to compute the pattern data density. As a result, the density computation processing section 103 divides the layout data stored in the input processing section 102 into lattice shape detection ranges.
Next, in step S101, the density computation processing section 103 performs computation of the pattern data density for each of the divided detection ranges.
Then, in step S102, the density computation processing section 103 judges if the pattern data density for each of the detection ranges is above 50%. That is to say, judges if the detection range is a pattern data density error region. At this time, in the case where the density computation processing section 103 judges that the detection range is a pattern data density error region, processing is advanced to step S103.
Next in step S103, the density computation processing section 103 makes the color of the region corresponding to the pattern data density error region in the layout data stored in the output processing section 104 different from that for other normal regions. Then, the output processing section 104 displays on the layout data, by means of the CRT, an image of the pattern data density error region, in a color which is clearly different compared to that for regions where the pattern data density is normal.
Furthermore, in step S102, the density computation processing section 103, in the case where the detection range is not a pattern data density error region, advances the processing to step S104.
Then, in step S104, the control section 100 judges if the density computation processing section 103 has computed the pattern data densities for all of the lattices in the detection range of the layout data stored in the input processing section 102, that is to say if the density computation processing section 103 has computed the pattern data density for all the detection ranges of the layout data, and performed judgment for pattern data density error regions for all of the detection ranges.
At this time, the control section 100, in the case where judgment has been performed with respect to the pattern data density error regions for all of the detection ranges, terminates the processing for the pattern data density detection, while in the case where the judgment for the pattern data density error regions for all of the detection ranges has not been performed, returns the processing to step S101, and continues the processing for the pattern data density detection.
However, with the above mentioned pattern data density inspection apparatus, since the above mentioned computation of the pattern data density, and the judgment of the pattern data density error region is performed by dividing the layout data as a detection range lattice (error judgment reference shape) of 400 xcexcm squares as shown in FIG. 12, based on the experimental results shown in FIG. 9, there is the disadvantage in that the detection accuracy of the pattern data density error range is low.
That is to say, when as shown in FIG. 12, the pattern data density inspection apparatus performs detection of pattern data density error regions for a detection range lattice of 400 xcexcm squares, in the case of a pattern data density error region R1, the pattern data density error region R1 overlaps the lattice of a divided detection range. Therefore, the pattern data density detection apparatus cannot detect the pattern data density error region R1 with the 400 xcexcm square detection range.
On the other hand, in the case of the pattern data density error region R2, since the pattern data density error region R2 exists over a lattice of four divided detection ranges, the pattern data density of the pattern data density error region R2 is averaged in the four detection ranges. As a result, since each of the four detection ranges do not reach a value of the pattern data density for the pattern data density error range, the pattern data density inspection apparatus detects this as a normal range, and hence cannot detect the pattern data density error region R2.
In order to deal with this, instead of a detection range of 400 xcexcm squares, it has been considered to use a detection range of 100 xcexcm squares so that a rounding error for the pattern data density error region does not occur. This 100 xcexcm square detection range, in order to detect regions of 400 xcexcm square or more which produce a global difference having an influence on reliability, is a value which is obtained as a minimum area having significance for computing the pattern data density based on the design rule when obtaining the graph of FIG. 9 and on the experimental results of FIG. 9, and this changes naturally in the case where the design rule differs.
As a result, as shown in FIG. 14, by detection using the detection range of 100 xcexcm squares, then compared to the case of the detection range of FIG. 12, in the pattern data density error region R5, in the region of a 400 xcexcm square, pattern data density error regions R5A of 100 xcexcm squares can be detected. Hence it can be seen that the detection accuracy for the pattern data density error region is improved compared to the case for the detection range of the 400 xcexcm squares.
However, in improving accuracy by making the detection range 100 xcexcm squares, a stand alone pattern data density error region R3 of a 100 xcexcm square, and a stand alone pattern data density error region R4 of 100 xcexcmxc3x97200 xcexcm are detected. However, with the stand alone pattern data density error regions R3 and R4, regions of an area greater than the 400 xcexcm square which produces the global difference having a height which is the cause of the drop in reliability, obtained from the experimental results shown in FIG. 9, deviate from the detection reference, being the pattern data density error region. Therefore, the inherent pattern data density error regions R3 and R4 are regions which should not be detected as images of pattern data density error regions in the detection results for the pattern data density.
Furthermore, even in the detection range for the above mentioned 100 xcexcm squares, in practice, the detection accuracy of the pattern data density error region R5 cannot be said to be sufficient. This is because for portions R5A less than a 100 xcexcm square and with high pattern data density connected to the pattern data density error region R5, since detection is limited to being carried out for the detection range of the 100 xcexcm square, detection of a high accuracy for these portions cannot be expected. Therefore, while regions where the pattern data density is high, can be detected by making the detection ranges less than the 100 xcexcm square, the pattern data density error regions R3 and R4 which are not judged as inherent pattern data density error regions become excessively detected. Therefore, the designer must perform correction operations while judging the places to be corrected, and the places not to be corrected. Hence a problem arises in that there is a drop in the efficiency of the correction operation for the layout pattern.
The present invention has come about under the above mentioned background, and provides a pattern density inspection apparatus which improves the detection accuracy of the pattern data density error region, and outputs detection results for a designer to efficiently perform a correction operation without performing detection of pattern data density error regions which do not require correction.
A pattern data density inspection apparatus according to the first aspect of the present invention comprises: a pattern data density computing device (for example, the data density computing section of the embodiment) for obtaining for each of predetermined distance displacements for overlapping detection ranges of a predetermined area, pattern data densities showing a ratio of a total area of pattern data for wiring inside these detection ranges to the area; a temporary error region detection device (for example, the error overlap removal processing section of the embodiment) for taking a logical sum of the detection ranges where the pattern data density is above a previously set threshold value, and obtaining a temporary pattern data density error region (for example, the temporary error region of the embodiment); and an error region detection device (for example, the error region width computation processing section of the embodiment) for making the temporary pattern data density error region (for example the aggregate temporary error region of the embodiment) of a shape completely containing a previously set pattern data density error figure in plan view, a pattern data density error region.
A pattern data density inspection apparatus according to a second aspect of the present invention is a pattern data density inspection apparatus according to the first aspect of the present invention, wherein an area of the pattern data for wiring which is less than a predetermined pattern width is excluded from the total area for obtaining the pattern data density.
A pattern data density inspection apparatus according to a third aspect of the present invention is a pattern data density inspection apparatus according to either one of the first and second aspects of the present invention, wherein the pattern data density computing device computes the pattern data density for each of the predetermined distance displacements of the detection ranges for either of an X direction and a Y direction.
A pattern data density inspection apparatus according to a fourth aspect of the present invention is a pattern data density inspection apparatus according to any one of the first through third aspects of the present invention, wherein there is provided an output device for outputting the pattern data density error region and another normal pattern data region, in different colors.
A pattern data density inspection method according to a fifth aspect of the present invention is a pattern data density inspection method having: a first step where a pattern data density computing device obtains for each of predetermined distance displacements for overlapping detection ranges of a predetermined area, a pattern data density showing a ratio of a total area of pattern data for wiring inside these detection ranges to the area; a second step where a temporary error region detection device takes a logical sum of the detection ranges where the pattern data density is above a previously set threshold value, and obtains a temporary pattern data density error region; and a third step where an error region detection device makes the temporary pattern data density error region of a shape completely containing a previously set pattern data density error figure in plan view, a pattern data density error region.
A pattern data density inspection method according to a sixth aspect of the present invention is a pattern data density inspection method according to the fifth aspect of the present invention, wherein an area of the pattern data for wiring which is less than a predetermined pattern width is excluded from the total area for obtaining the pattern data density.
A pattern data density inspection method according to a seventh aspect of the present invention is a pattern data density inspection method according to either one of the fifth and sixth aspects of the present invention, wherein the pattern data density computing device computes the pattern data density for each of the predetermined distance displacements of the detection ranges for either of an X direction and a Y direction.
A pattern data density inspection method according to an eighth aspect of the present invention is a pattern data density inspection method according to any one of the fifth through seventh aspects of the present invention, wherein there is provided an output device for outputting the pattern data density error region and another normal pattern data region, in different colors.
A recording medium according to a ninth aspect of the invention is a computer readable recording medium on which is recorded a pattern data density inspection program for performing pattern data density inspection using a pattern data density inspection apparatus according to the first aspects of the present invention, wherein the pattern data density inspection program performs on a computer: a process where a pattern data density computing device while effecting displacement for overlapping detection ranges of a predetermined area, obtains pattern data densities showing a ratio of a total area of pattern data for wiring inside these detection ranges to the area; a process where a temporary error region detection device takes a logical sum of the detection ranges where the pattern data density is above a previously set threshold value, and obtains a temporary pattern data density error region; and a process where an error region detection device makes the temporary pattern data density error region of a shape completely containing a previously set pattern data density error figure in plan view, a pattern data density error region.